if have makefile e.g.:
foo.o: foo.c a.h b.h c.h cc -c foo.c -o foo.o now, in other part of makefile, want prerequsites of foo.o, i'd $^ in recipe. like:
$(info $(call get_target_prereqs(foo.o))) # prints "foo.c a.h b.h c.h" basically, have dependency files (generated -m) object files, , there want list of header files included given object.
i'm hoping more or less pure make solution, , not sed script parses *.d files , outputs makefile fragments.
if want print prerequsites, can use $^
.pony: all: b c @echo $^ a: b: c: 