for practice, attempted make vhdl code run rotary encoder hardware. full debounce, quadrature decoder , up/down counter codes.
unfortunately, when running simulation testbench, results disappointing decided each block needs analysed separately. debounce code, created symbol file , produced circuit below
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while attempting debounce testbench signal in simulation, found out results terrible believe missing something.
(clickable)
the vhdl code encoder block can found here :
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debounce_a generic( counter_size : integer := 8); --counter size (8 bits gives 51.6 5mhz clock) port( clk : in std_logic; --input clock bounce_a : in std_logic; --input signal debounced result : out std_logic); --debounced signal end debounce_a; architecture logic of debounce_a signal flipflops : std_logic_vector(1 downto 0); --input flip flops signal counter_set : std_logic; --sync reset 0 signal counter_out : std_logic_vector(counter_size downto 0) := (others => '0'); --counter output begin counter_set <= flipflops(0) xor flipflops(1); --determine when start/reset counter process(clk) -- occurs within clock event begin if(clk'event , clk = '1') -- can rising_edge(clk) flipflops(0) <= bounce_a; -- adresses signal set value flipflops(1) <= flipflops(0); if(counter_set = '1') --reset counter because input changing counter_out <= (others => '0'); --set bits '0' elsif(counter_out(counter_size) = '0') --stable input time not yet met counter_out <= counter_out + 1; else --stable input time met result <= flipflops(1); end if; end if; end process; end logic; it filled brim unwanted logic because had limited idea of doing , took friends general debounce code , edited try , fit specific needs.
if needed willing provide. feel it's pretty basic error need sort of help.
here on testbench code used if helps identify toggling properties :
library ieee; use ieee.std_logic_1164.all; entity decodeblock_vhd_tst end decodeblock_vhd_tst; architecture decodeblock_arch of decodeblock_vhd_tst -- constants constant clk_period : time := 20 ns; constant num_clk_cycles : integer := 100; -- signals signal b_input : std_logic; signal b_output : std_logic; signal clock_50 : std_logic := '0'; component decodeblock port ( b_input : in std_logic; b_output : out std_logic; clock_50 : in std_logic ); end component; begin i1 : decodeblock port map ( -- list connections between master ports , signals b_input => b_input, b_output => b_output, clock_50 => clock_50 ); init : process -- variable declarations begin b_input <= '0', '1' after 1.1 ns, '0' after 2.9 ns, '1' after 5.1 ns, '0' after 7.6 ns, '1' after 9.9 ns, '0' after 12.5 ns, '1' after 15.4 ns, '0' after 18.6 ns, '1' after 22.1 ns, '0' after 25.9 ns, '1' after 29.7 ns, '0' after 33.8 ns, '1' after 38.2 ns; -- variable declarations in 1 num_clk_cycles loop clock_50 <= not clock_50; wait clk_period/2; clock_50 <= not clock_50; wait clk_period/2; end loop; wait; end process init; : process -- optional sensitivity list -- ( ) -- variable declarations begin -- code executes every event on sensitivity list wait; end process always; end decodeblock_arch;
