my verilog testbench never stop -


professor gives code below. , have figure out why never stop.

module tb_problem1();

reg a, b, c, d, e; wire x; reg [4:0] ins;  problem1 dut(a, b, c, d, e, x);  initial begin     ins = 0;     while(ins < 32) begin         {a, b, c, d, e} = ins;         #20;         ins = ins + 1;     end end  endmodule 

is because need ins = ins+1'b1; ?

a 5-bit unsigned value supports range 0 31. adding 1 31 drop msb , return 0. therefore value of 32 never reached.

try making ins 6-bit value.