i programming alu in vhdl , using cyclone ii board. need compare 2 std_logic_vectors see if 1 greater another. used greater (>) in condition don't know if fpga can synthesize operator. there workaround compare 2 vectors without using ">" , synthesize it?
the datatype std_logic_vector set of bits (with 9 values ...), doesn't define arithmetic behavior.
to use arithmetic operations addition, multiplication or comparisons intended "greater than", need datatype example unsigned or signed. these types define additional arithmetic operations. when declare signals (un)signed, vhdl know additional operators , synthesizer infer correct hardware.
-- declare signals in declarative region signal mysignal1 : unsigned(7 downto 0); signal mysignal2 : unsigned(7 downto 0); signal greater : boolean; -- compare them greater <= mysignal1 > mysignal2; 