i'm trying make 8-bit sequential multiplier on quartus ii. did simulations of blocks, 1 showing error on vwf simulation. sum_reg block it's doing infinite shift in small time interval.
in "dark blue" part of waveform simulation, on o_dout, it's when shift gones infinite until msb goes lsb. image below shows happens in dark blue part of simulation:
someone know what's happen?
below code:
sum register(where simulation goes wrong):
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sum_register port ( i_din : in unsigned(8 downto 0); i_load : in std_logic; i_clear : in std_logic; i_shift : in std_logic; o_dout : buffer unsigned(15 downto 0) ); end sum_register; architecture arch_1 of sum_register begin process(i_clear,i_load,i_shift, i_din) begin if (i_clear = '1') o_dout <= "0000000000000000"; elsif (i_load = '1') o_dout(15 downto 7) <= i_din; elsif (i_shift = '1') o_dout <= o_dout srl 1; end if; end process; end arch_1;
you need use clock signal in circuit make synchronous, need input in entity this:
i_clock : in std_ulogic; after need make process sensitivy clock:
process(i_clock) and architecture change this:
architecture arch_1 of sum_register signal r_dout : unsigned(15 downto 0); begin process(i_clock) begin if rising_edge(i_clock) if (i_clear = '1') r_dout <= "0000000000000000"; elsif (i_load = '1') r_dout(15 downto 8) <= i_din; elsif (i_shift = '1') r_dout <= r_dout srl 1; end if; end if; end process; o_dout <= r_dout; end arch_1; with architecture need unsigned signal make atribution output o_dout, can change o_dout output output type again (not buffer).
note: clock signal needs same blocks!
